Spin-Orbit Torque magnetic memory (SOT-MRAM) is the only non-volatile memory technology fast enough to be used closest to the computing unit as a replacement for SRAM-type memories, in order to increase the performance of electronic circuits while greatly reducing their energy consumption.
However, in the case of SOT-MRAM, where the magnetization is said to be perpendicular, it has been shown that the writing probability can collapse or even oscillate at high current.
A team from SPINTEC, in collaboration with the company Antaios stemming from the laboratory, has quantified this harmful phenomenon in SOT-MRAM based on β W/CoFeB/MgO layers. By measuring the Write Error Rate (WER), it proved that this phenomenon is not random but on the contrary deterministic.
The researchers performed so-called macrospin numerical simulations (uniform magnetization), based on experimental parameters, which reproduce the WER maps and allow explaining the mechanism. By injecting a high-amplitude current pulse, the magnetization of the SOT-MRAM tilts in the plane, at 90° relative to its initial direction along the -z axis (corresponding to bit 0).
However, this dynamic position is unstable, and at the end of the pulse, during relaxation, thermal fluctuations can bring the magnetization back to the initial -z direction, causing the writing to fail by leaving the bit at 0, instead of orienting it in the +z direction to write bit 1.
The simple solution, without needing to resort to exotic materials and physical effects, is to modify the shape of the current pulse. By extending the duration of its decay, the current continues to act on the magnetization during relaxation, allowing it to move away from its unstable equilibrium position in a controlled manner. Thus, for pulses with a duration of 10ns, it is enough to go from 2ns to 4ns of fall time to avoid the back-switching effect.
This solution has been demonstrated on an individual SOT-MRAM memory cell for which no writing error was detected after hundreds of thousands of cumulative writing tests (WER < 2.10
−6).
(a) Increase in the writing window of a simplified memory point (minimum WER), as a function of the decay duration of the electrical pulse.
(b) Validation of this solution on a complete and functional memory cell.
Beyond these results, these simulations pave the way for memory circuit design tools integrating back switching. The next objectives to achieve for the industrial development of this technology are obtaining writing using only a current as well as reducing this current.